Improvements in NAND flash memory technology have led to reduced solid state device geometries and increased bit density of NAND flash memories. However, the increased bit density results in an increase in error rates of data decoded from such memories. Accordingly, there has been an increase in emphasis on improving the error correction capability provided by NAND flash memory controllers. Error correction is necessary due to the nature of the technology where reliability and endurance problems increase as flash memory density increases.
A flash memory is generally organized in units of pages which are the smallest unit which are individually programmable. A block, which is the smallest unit which can be erased, is composed of multiple pages. A page of memory is provided with a spare area, which is used for the extra bits required for error-correcting code ECC, as well as other functions such as bits for keeping track of wear leveling and other metadata. The spare area was originally sized to be large enough to accommodate enough bits to provide for ECC such as BCH (Bose Chaudhuri Hocqenghem) type codes for error correction given the expected error rates of memories at the time. BCH error correction codes are extensively used to correct read errors in NAND flash memories as they can be flexibly designed to correct a precise number of errors in a block of data (meaning that data block of a given size and expected error rate can be exactly reconstructed with certainty), wherever and however they may occur (i.e. randomly distributed, in fixed patterns or in bursts). They are also relatively simple to implement decoders. As such, BCH codes could be specifically designed to work with a given flash memory data page and spare area size.
As long as the number of errors in the memory page does not exceed the correction capability of the BCH code, the original data should be decodable by the BCH code. However, such convergence places a greater requirement burden on the system processor to cope with greater error rates in more dense NAND flash memories, along with greater requirements for longer memory endurance in enterprise computing applications as opposed to consumer applications. This has meant that BCH codes have become incapable of being economically or feasibly scaled to meet the new data requirements with higher error rates. In other words, as NAND densities increase, the bit error rates (BER) in each memory cell also increase accordingly, making BCH decoding less ideal due to the limitation imposed by the maximum error rate correction capability of the BCH code.